
`include "defines.v"
//----------------------------------------------------------------
//Module Name : SimTop.v
//Description of module:
// 
//----------------------------------------------------------------
//Designer:	Tang Pengyu
//Date: 2021/09/10	  
//----------------------------------------------------------------

`define AXI_TOP_INTERFACE(name) io_memAXI_0_``name

module SimTop(
    input                               clock,
    input                               reset,

    input  [63:0]                       io_logCtrl_log_begin,
    input  [63:0]                       io_logCtrl_log_end,
    input  [63:0]                       io_logCtrl_log_level,
    input                               io_perfInfo_clean,
    input                               io_perfInfo_dump,

    output                              io_uart_out_valid,
    output [7:0]                        io_uart_out_ch,
    output                              io_uart_in_valid,
    input  [7:0]                        io_uart_in_ch,

    input                               `AXI_TOP_INTERFACE(aw_ready),
    output                              `AXI_TOP_INTERFACE(aw_valid),
    output [`AXI_ADDR_WIDTH-1:0]        `AXI_TOP_INTERFACE(aw_bits_addr),
    output [2:0]                        `AXI_TOP_INTERFACE(aw_bits_prot),
    output [`AXI_ID_WIDTH-1:0]          `AXI_TOP_INTERFACE(aw_bits_id),
    output [`AXI_USER_WIDTH-1:0]        `AXI_TOP_INTERFACE(aw_bits_user),
    output [7:0]                        `AXI_TOP_INTERFACE(aw_bits_len),
    output [2:0]                        `AXI_TOP_INTERFACE(aw_bits_size),
    output [1:0]                        `AXI_TOP_INTERFACE(aw_bits_burst),
    output                              `AXI_TOP_INTERFACE(aw_bits_lock),
    output [3:0]                        `AXI_TOP_INTERFACE(aw_bits_cache),
    output [3:0]                        `AXI_TOP_INTERFACE(aw_bits_qos),
    
    input                               `AXI_TOP_INTERFACE(w_ready),
    output                              `AXI_TOP_INTERFACE(w_valid),
    output [`AXI_DATA_WIDTH-1:0]        `AXI_TOP_INTERFACE(w_bits_data)         [3:0],
    output [`AXI_DATA_WIDTH/8-1:0]      `AXI_TOP_INTERFACE(w_bits_strb),
    output                              `AXI_TOP_INTERFACE(w_bits_last),
    
    output                              `AXI_TOP_INTERFACE(b_ready),
    input                               `AXI_TOP_INTERFACE(b_valid),
    input  [1:0]                        `AXI_TOP_INTERFACE(b_bits_resp),
    input  [`AXI_ID_WIDTH-1:0]          `AXI_TOP_INTERFACE(b_bits_id),
    input  [`AXI_USER_WIDTH-1:0]        `AXI_TOP_INTERFACE(b_bits_user),

    input                               `AXI_TOP_INTERFACE(ar_ready),
    output                              `AXI_TOP_INTERFACE(ar_valid),
    output [`AXI_ADDR_WIDTH-1:0]        `AXI_TOP_INTERFACE(ar_bits_addr),
    output [2:0]                        `AXI_TOP_INTERFACE(ar_bits_prot),
    output [`AXI_ID_WIDTH-1:0]          `AXI_TOP_INTERFACE(ar_bits_id),
    output [`AXI_USER_WIDTH-1:0]        `AXI_TOP_INTERFACE(ar_bits_user),
    output [7:0]                        `AXI_TOP_INTERFACE(ar_bits_len),
    output [2:0]                        `AXI_TOP_INTERFACE(ar_bits_size),
    output [1:0]                        `AXI_TOP_INTERFACE(ar_bits_burst),
    output                              `AXI_TOP_INTERFACE(ar_bits_lock),
    output [3:0]                        `AXI_TOP_INTERFACE(ar_bits_cache),
    output [3:0]                        `AXI_TOP_INTERFACE(ar_bits_qos),
    
    output                              `AXI_TOP_INTERFACE(r_ready),
    input                               `AXI_TOP_INTERFACE(r_valid),
    input  [1:0]                        `AXI_TOP_INTERFACE(r_bits_resp),
    input  [`AXI_DATA_WIDTH-1:0]        `AXI_TOP_INTERFACE(r_bits_data)         [3:0],
    input                               `AXI_TOP_INTERFACE(r_bits_last),
    input  [`AXI_ID_WIDTH-1:0]          `AXI_TOP_INTERFACE(r_bits_id),
    input  [`AXI_USER_WIDTH-1:0]        `AXI_TOP_INTERFACE(r_bits_user)
);

	wire aw_ready;
    wire aw_valid;
    wire [`AXI_ADDR_WIDTH-1:0] aw_addr;
    wire [2:0] aw_prot;
    wire [`AXI_ID_WIDTH-1:0] aw_id;
    wire [`AXI_USER_WIDTH-1:0] aw_user;
    wire [7:0] aw_len;
    wire [2:0] aw_size;
    wire [1:0] aw_burst;
    wire aw_lock;
    wire [3:0] aw_cache;
    wire [3:0] aw_qos;
    wire [3:0] aw_region;

    wire w_ready;
    wire w_valid;
    wire [`AXI_DATA_WIDTH-1:0] w_data;
    wire [`AXI_DATA_WIDTH/8-1:0] w_strb;
    wire w_last;
    wire [`AXI_USER_WIDTH-1:0] w_user;
    
    wire b_ready;
    wire b_valid;
    wire [1:0] b_resp;
    wire [`AXI_ID_WIDTH-1:0] b_id;
    wire [`AXI_USER_WIDTH-1:0] b_user;

    wire ar_ready;
    wire ar_valid;
    wire [`AXI_ADDR_WIDTH-1:0] ar_addr;
    wire [2:0] ar_prot;
    wire [`AXI_ID_WIDTH-1:0] ar_id;
    wire [`AXI_USER_WIDTH-1:0] ar_user;
    wire [7:0] ar_len;
    wire [2:0] ar_size;
    wire [1:0] ar_burst;
    wire ar_lock;
    wire [3:0] ar_cache;
    wire [3:0] ar_qos;
    wire [3:0] ar_region;
    
    wire r_ready;
    wire r_valid;
    wire [1:0] r_resp;
    wire [`AXI_DATA_WIDTH-1:0] r_data;
    wire r_last;
    wire [`AXI_ID_WIDTH-1:0] r_id;
    wire [`AXI_USER_WIDTH-1:0] r_user;

    assign ar_ready                                 = `AXI_TOP_INTERFACE(ar_ready);
    assign `AXI_TOP_INTERFACE(ar_valid)             = ar_valid;
    assign `AXI_TOP_INTERFACE(ar_bits_addr)         = ar_addr;
    assign `AXI_TOP_INTERFACE(ar_bits_prot)         = ar_prot;
    assign `AXI_TOP_INTERFACE(ar_bits_id)           = ar_id;
    assign `AXI_TOP_INTERFACE(ar_bits_user)         = ar_user;
    assign `AXI_TOP_INTERFACE(ar_bits_len)          = ar_len;
    assign `AXI_TOP_INTERFACE(ar_bits_size)         = ar_size;
    assign `AXI_TOP_INTERFACE(ar_bits_burst)        = ar_burst;
    assign `AXI_TOP_INTERFACE(ar_bits_lock)         = ar_lock;
    assign `AXI_TOP_INTERFACE(ar_bits_cache)        = ar_cache;
    assign `AXI_TOP_INTERFACE(ar_bits_qos)          = ar_qos;
    
    assign `AXI_TOP_INTERFACE(r_ready)              = r_ready;
    assign r_valid                                  = `AXI_TOP_INTERFACE(r_valid);
    assign r_resp                                   = `AXI_TOP_INTERFACE(r_bits_resp);
    assign r_data                                   = `AXI_TOP_INTERFACE(r_bits_data)[0];
    assign r_last                                   = `AXI_TOP_INTERFACE(r_bits_last);
    assign r_id                                     = `AXI_TOP_INTERFACE(r_bits_id);
    assign r_user                                   = `AXI_TOP_INTERFACE(r_bits_user);
	
	assign aw_ready 								= `AXI_TOP_INTERFACE(aw_ready);
	
	assign `AXI_TOP_INTERFACE(aw_valid) 			= aw_valid;
	assign `AXI_TOP_INTERFACE(aw_bits_addr)			= aw_addr;
	assign `AXI_TOP_INTERFACE(aw_bits_prot)			= aw_prot;
	assign `AXI_TOP_INTERFACE(aw_bits_len)			= aw_len;
	assign `AXI_TOP_INTERFACE(aw_bits_size)			= aw_size;
	assign `AXI_TOP_INTERFACE(aw_bits_burst)		= aw_burst;
	assign `AXI_TOP_INTERFACE(aw_bits_user)			= aw_user;
	assign `AXI_TOP_INTERFACE(aw_bits_lock)			= aw_lock;
	assign `AXI_TOP_INTERFACE(ar_bits_cache)		= aw_cache;
	assign `AXI_TOP_INTERFACE(aw_bits_qos)			= aw_qos;
	assign `AXI_TOP_INTERFACE(aw_bits_id)			= aw_id;
	
	assign w_ready									= `AXI_TOP_INTERFACE(w_ready);
	
	assign `AXI_TOP_INTERFACE(w_valid)				= w_valid;
	assign `AXI_TOP_INTERFACE(w_bits_data) [3]		= 'd0;
	assign `AXI_TOP_INTERFACE(w_bits_data) [2]		= 'd0;
	assign `AXI_TOP_INTERFACE(w_bits_data) [1]		= 'd0;
	assign `AXI_TOP_INTERFACE(w_bits_data) [0]		= w_data;
	assign `AXI_TOP_INTERFACE(w_bits_strb)			= w_strb;
	assign `AXI_TOP_INTERFACE(w_bits_last)			= w_last;
	
	assign `AXI_TOP_INTERFACE(b_ready)				= b_ready;
	
	assign b_valid									= `AXI_TOP_INTERFACE(b_valid);
	assign b_resp									= `AXI_TOP_INTERFACE(b_bits_resp);	
	assign b_id										= `AXI_TOP_INTERFACE(b_bits_id);
	assign b_user									= `AXI_TOP_INTERFACE(b_bits_user);
	

wire	load_clint_en;
wire	clint_w_ena;
wire	[63:0]	load_store_addr;
wire	[63:0]	store_clint_data;
wire	time_overstep;
wire	[63:0]	load_clint_data;
wire	load_clint_en_exe;
wire	[63:0]	load_clint_addr_exe;
wire	[63:0]	load_clint_data_exe;

ysyx_210195	ysyx_210195(
  .clock(clock),
  .reset(reset),
//  input         io_interrupt,
  .io_master_awready(aw_ready),
  .io_master_awvalid(aw_valid),
  .io_master_awaddr(aw_addr),
  .io_master_awid(aw_id),
  .io_master_awlen(aw_len),
  .io_master_awsize(aw_size),
  .io_master_awburst(aw_burst),
  .io_master_wready(w_ready),
  .io_master_wvalid(w_valid),
  .io_master_wdata(w_data),
  .io_master_wstrb(w_strb),
  .io_master_wlast(w_last),
  .io_master_bready(b_ready),
  .io_master_bvalid(b_valid),
  .io_master_bresp(b_resp),
  .io_master_bid(b_id),
  .io_master_arready(ar_ready),
  .io_master_arvalid(ar_valid),
  .io_master_araddr(ar_addr),
  .io_master_arid(ar_id),
  .io_master_arlen(ar_len),
  .io_master_arsize(ar_size),
  .io_master_arburst(ar_burst),
  .io_master_rready(r_ready),
  .io_master_rvalid(r_valid),
  .io_master_rresp(r_resp),
  .io_master_rdata(r_data),
  .io_master_rlast(r_last),
  .io_master_rid(r_id)
/*
  output        io_slave_awready,
  input         io_slave_awvalid,
  input  [31:0] io_slave_awaddr,
  input  [3:0]  io_slave_awid,
  input  [7:0]  io_slave_awlen,
  input  [2:0]  io_slave_awsize,
  input  [1:0]  io_slave_awburst,
  output        io_slave_wready,
  input         io_slave_wvalid,
  input  [63:0] io_slave_wdata,
  input  [7:0]  io_slave_wstrb,
  input         io_slave_wlast,
  input         io_slave_bready,
  output        io_slave_bvalid,
  output [1:0]  io_slave_bresp,
  output [3:0]  io_slave_bid,
  output        io_slave_arready,
  input         io_slave_arvalid,
  input  [31:0] io_slave_araddr,
  input  [3:0]  io_slave_arid,
  input  [7:0]  io_slave_arlen,
  input  [2:0]  io_slave_arsize,
  input  [1:0]  io_slave_arburst,
  input         io_slave_rready,
  output        io_slave_rvalid,
  output [1:0]  io_slave_rresp,
  output [63:0] io_slave_rdata,
  output        io_slave_rlast,
  output [3:0]  io_slave_rid
*/
);
/*	
ysyx_210195_cpu	ysyx_210195_CPU(
	.clock(clock),
    .reset(reset),

//to slave
	//MASTER write addr
	.aw_ready_i(aw_ready),			//slave -> master,ready to receive write address
	.aw_valid_o(aw_valid),			//master -> slave,write address valid
	.aw_addr_o(aw_addr),		//write sddress
	.aw_id_o(aw_id),			//write address channel ID
	.aw_user_o(aw_user),		//自定义
	.aw_prot_o(aw_prot),				//access permissions
	.aw_len_o(aw_len),			//burst lenth = aw_len + 1
	.aw_size_o(aw_size),			//本次burst中，一次transferde的字节数
	.aw_burst_o(aw_burst),			//burst_type
	.aw_lock_o(aw_lock),
	.aw_cache_o(aw_cache),			//memory types
	.aw_qos_o(aw_qos),			//Quality of service identifier for a write transaction
	.aw_region_o(aw_region),		//多接口时用
	
	//master write data
	.w_ready_i(w_ready),
	.w_valid_o(w_valid),
	.w_data_o(w_data),
	.w_strb_o(w_strb),				//标志有效位
	.w_last_o(w_last),						//标志最后一次传输
	.w_user_o(w_user),
	
	//write response
	.b_ready_o(b_ready),
	.b_valid_i(b_valid),
	.b_resp_i(b_resp),
	.b_id_i(b_id),
	.b_user_i(b_user),
	
	//read address channel
	.ar_ready_i(ar_ready),
	.ar_valid_o(ar_valid),
	.ar_addr_o(ar_addr),
	.ar_prot_o(ar_prot),
	.ar_id_o(ar_id),			//read address channel identifier
	.ar_user_o(ar_user),
	.ar_len_o(ar_len),
	.ar_size_o(ar_size),
	.ar_burst_o(ar_burst),
	.ar_lock_o(ar_lock),
	.ar_cache_o(ar_cache),
	.ar_qos_o(ar_qos),
	.ar_region_o(ar_region),
	
	//read data channel
	.r_ready_o(r_ready),
	.r_valid_i(r_valid),
	.r_resp_i(r_resp),
	.r_data_i(r_data),
	.r_last_i(r_last),
	.r_id_i(r_id),
	.r_user_i(r_user),
	
	//clint
	.load_clint_en(load_clint_en),
	.clint_w_ena(clint_w_ena),
	.load_store_addr(load_store_addr),
	.store_clint_data(store_clint_data),
	.load_clint_en_exe(load_clint_en_exe),
	.load_clint_addr_exe(load_clint_addr_exe),
	
	.time_overstep(time_overstep),
	.load_clint_data_exe(load_clint_data_exe),
	.load_clint_data(load_clint_data)

);

ysyx_210195_clint_reg	ysyx_210195_CLINT(
	.clk(clock),
	.rst(reset),
	.load_clint_en(load_clint_en),
	.clint_w_ena(clint_w_ena),
	.load_store_addr(load_store_addr),
	.store_clint_data(store_clint_data),
	.load_clint_en_exe(load_clint_en_exe),
	.load_clint_addr_exe(load_clint_addr_exe),
	
	.load_clint_data(load_clint_data),
	.load_clint_data_exe(load_clint_data_exe),
	.time_overstep(time_overstep)
	
	
);

*/
	
endmodule